1. Field of the Invention
The present invention relates to a method for manufacturing a field effect transistor (FET), and more particularly to a method for manufacturing a Schottky gate field effect transistor (MESFET).
2. Related Background Art
In a MESFET, it has been proposed to make an interval between a drain n.sup.+ layer and a gate electrode larger than an interval between a source n.sup.+ layer and the gate electrode so that a drain break-down voltage is raised while a serial resistance is kept low to attain a low drain conductance.
As a manufacturing method for such an asymmetric structure MESFET, a method which uses a multi-layer dummy gate has been known. JP-A-61-194781 shows one manufacturing method therefore, in which a bi-layer dummy gate is formed, a metal film such as aluminum (Al) is deposited on the surface of the dummy gate except a side wall facing the drain and a vicinity thereof, the lower layer of the dummy gate facing the drain is etched using the metal film as a mask to form an asymmetric T-shaped dummy gate structure, and the asymmetric structure MESFET is manufactured by using the asymmetric dummy gate.
In the related art, the dummy gate must be of multi-layer structure and it must be asymmetric T-shaped dummy gate structure. In order to form the asymmetric T-shaped dummy gate, a complex process including partial vapor deposition of the Al metal film, etching of only one side of the side walls of the lower layer of the dummy gate, and removal of the Al metal film is required.